This invention relates to a switching power supply circuit incorporated as a power supply in various electronic apparatus.
Various switching power supply circuits are widely known including, for example, a switching power supply circuit of the flyback converter type or the forward converter type. The switching converters of the types mentioned are restricted in suppression of switching noise because the switching operation waveform is a rectangular waveform. Further, it is known that the switching converters are limited in improvement in the power conversion efficiency from their operation characteristics.
Therefore, various switching power supply circuits which use a resonance converter have been proposed and placed into practical use. The resonance converters are advantageous in that a high power conversion efficiency can be achieved readily and low noise can be achieved because the switching operation waveform thereof is a sine waveform. The resonance converters are advantageous also in that they can be composed of a comparatively small number of components.
FIG. 23 shows an example of a conventional switching power supply circuit which includes a resonance converter. The power supply circuit includes a combination of a current resonance converter of the separately excited type and a partial voltage resonance circuit.
Referring to FIG. 23, the power supply circuit shown includes a full-wave rectification smoothing circuit for an ac input voltage VAC. The full-wave rectification smoothing circuit includes a bridge rectification circuit (rectification circuit section) Di and a single smoothing capacitor Ci. A rectified smoothed voltage (dc input voltage) Ei is obtained across the smoothing capacitor Ci by a full-wave rectification operation of the bridge rectification circuit Di and the smoothing capacitor Ci. The rectified smoothed voltage Ei has a level equal to the ac input voltage VAC.
The current resonance converter which receives the dc input voltage to perform a switching operation includes two switching elements Q1, Q2 each in the form of a MOS-FET connected in half-bridge connection. Damper diodes DD1, DD2 each in the form of a body diode are connected in parallel in directions shown in FIG. 23 between the drains and the sources of the switching elements Q1, Q2, respectively.
A partial resonance capacitor Cp is connected in parallel between the drain and the source of the switching element Q2. The capacitance of the partial resonance capacitor Cp and the leakage inductance L1 of a primary winding N1 form a parallel resonance circuit (partial voltage resonance circuit). Thus, a partial voltage resonance operation wherein voltage resonance is exhibited only upon turning off of the switching elements Q1, Q2 is obtained.
In the power supply circuit, in order to drive the switching elements Q1, Q2 for switching, an oscillation and drive circuit 2 is provided which may be formed typically from an IC for universal use. The oscillation and drive circuit 2 includes an oscillation circuit and a drive circuit. The oscillation circuit and the drive circuit cooperatively generate a drive signal (gate voltage) of a required frequency to be applied to the gates of the switching elements Q1, Q2. Consequently, the switching elements Q1, Q2 perform a switching operation wherein they alternately switch on/off in a required switching frequency.
An insulating converter transformer PIT transmits a switching output of the switching elements Q1, Q2 to the secondary side. The primary winding N1 of the insulating converter transformer PIT is connected at one end thereof to a node (switching output point) between the source of the switching element Q1 and the drain of the switching element Q2 through a series connection of a primary side series resonance capacitor C1 so that the switching output is transmitted.
The primary winding N1 is connected at the other end thereof to the primary side ground.
The capacitance of the series resonance capacitor C1 and the leakage inductance L1 of the insulating converter transformer PIT including the primary winding N1 form a primary side series resonance circuit for achieving operation of the current resonance type as operation of the primary side switching converter.
Thus, the primary side switching converter described above provides operation of the current resonance type by the primary side series resonance circuit (L1-C1) and partial voltage resonance operation by the partial voltage resonance circuit (Cp//L1) described hereinabove.
In other words, the power supply circuit shown in FIG. 23 has a configuration which includes a combination of a resonance circuit for forming a primary side switching converter as that of the resonance type with another resonance circuit. In the present specification, a switching converter of the type just described is referred to as composite resonance converter.
Though not shown in the drawings, the insulating converter transformer PIT includes an EE type core which includes a combination of E type cores typically made of a ferrite material. A wiring receiving portion of the insulating converter transformer PIT is divided into winding receiving portions for the primary side and the secondary side, and the primary winding N1 and a secondary winding (N2A and N2B) described below are wound on a central magnetic leg of the EE type core.
The secondary winding of the insulating converter transformer PIT has a center tap and is therefore divided into two secondary windings N2A, N2B. An alternating voltage corresponding to a switching output transmitted to the primary winding N1 is excited in each of the secondary windings N2A, N2B.
The center tap between the secondary windings N2A, N2B is connected to the secondary side ground. A full-wave rectification circuit is connected to the secondary windings N2A, N2B and includes rectification diodes D01, D02 and a smoothing capacitor C0. Consequently, a secondary side dc output voltage E0 is obtained as a voltage across the smoothing capacitor C0. The secondary side dc output voltage E0 is supplied to a load not shown and is dividedly inputted also as a detection voltage for a control circuit 1 described below.
The control circuit 1 supplies a detection output corresponding to a level variation of the secondary side dc output voltage E0 to the oscillation and drive circuit 2. The oscillation and drive circuit 2 drives the switching elements Q1, Q2 with a switching frequency which varies in response to the detection output of the control circuit 1 inputted thereto. As the switching frequency of the switching elements Q1, Q2 is varied in this manner, the level of the secondary side dc output voltage is stabilized.
Operation waveforms of the power supply circuit having the circuit configuration described above with reference to FIG. 23 where the power supply circuit is configured so as to be ready for load conditions of low voltage and high current are shown in FIG. 24. The operation waveforms of FIG. 24 were obtained by performing a measurement under the conditions of the ac input voltage VAC=100 V and the load power Po=100 W. Further, as the conditions of low voltage and high current, the secondary side dc voltage Eo is Eo=5 V and the primary side series resonance current Io which is switching current of the primary side switching converter is Io=25 A.
In order to obtain a result of the experiment based on the operation waveforms shown in FIG. 24, part elements and so forth of the power supply circuit were selected under the following conditions.
First, the numbers of turns of the secondary windings N2A, N2B and the primary winding N1 were set so that the induced voltage level per one turn (1 T) of the secondary side winding might be 5 V/T, and particularly the secondary windings N2A, N2B and the primary winding N1 were set to N2A=N2B=1 T and N1=30 T, respectively.
Further, a gap of approximately 1.0 mm was formed in the central magnetic leg of the EE type core of the insulating converter transformer PIT so that a coupling coefficient of approximately 0.85 was obtained between the primary winding N1 and the secondary windings N2A, N2B.
Further, the primary side series resonance capacitor C1 and the partial voltage resonance capacitor Cp were set to C1=0.068 μF and Cp=330 μF, respectively, and a Schottky diode of 50 A/40 V was selected for the rectification diodes Do1, Do2.
In the waveform diagram of FIG. 24, the voltage V1 across the switching element Q2 corresponds to on/off states of the switching element Q2. In short, the waveform of the voltage V1 has a rectangular waveform which exhibits the 0 level within a period T2 within which the switching element Q2 is on and has a predetermined level clamped within another period T1 within which the switching element Q2 is off. Then, the switching current IDS2 which flows through the switching element Q2//damper diode DD2 exhibits a waveform which exhibits a negative polarity upon turning on of the switching element Q2 as the switching current IDS2 flows through the damper diode DD2 as seen within a period T2 but exhibits the 0 level upon turning off of the switching element Q2 as the switching current IDS2 flows from the drain to the source of the switching element Q2 because of the positive polarity within another period T1.
Meanwhile, the switching element Q1 performs a switching operation such that it switches on/off alternately relative to the switching element Q2. Therefore, the switching current IDS1 which flows through the switching element Q1//damper diode DD1 has a waveform having a phase shifted by 180° with respect to the switching current IDS2.
Thus, the primary side series resonance current Io which flows through the primary side series resonance circuit (C1-L1) connected between the switching output point of the switching elements Q1, Q2 and the primary side ground has a waveform formed by combining a sine wave component of the resonance current of the primary side series resonance circuit (C1-L1) and a sawtooth waveform component generated by exciting inductance of the primary winding N1. The waveform corresponds to a composite waveform of the switching current IDS1 and the switching current IDS2.
The load power Po=100 W which is a measurement condition then is a heavy load condition proximate to a maximum load as a load condition with which the power supply circuit shown in FIG. 23 is compatible. However, in a condition wherein the load is in a heavy load tendency in a compatible load power range, the rectification current on the secondary side exhibits a discontinuous mode.
Here, in a configuration wherein the switching frequency is variably controlled to stabilize the secondary side dc output voltage Eo in such a manner as described hereinabove, for example, where the load is in a light load tendency, such control as to raise the switching frequency is performed to achieve stabilization. In this state, the rectification circuit on the secondary side operates in a continuous mode wherein the period within which the secondary side rectification current flows through the secondary side smoothing capacitor continues and does not include a period within which the secondary side rectification current stops.
On the other hand, where the load enters a heavy load condition as described above and the level of the secondary side dc output voltage Eo enters a dropping tendency, control is performed so as to lower the switching frequency of the primary side. According to this control, a discontinuous mode is entered wherein the secondary side rectification current does not flow continuously through the secondary side smoothing capacitor to produce a current discontinuous period.
In particular, the secondary winding voltage V2 generated in the secondary winding N2A in such a heavy load condition as described above exhibits a waveform wherein the secondary winding voltage V2 is clamped at a predetermined absolute value level only within a period within which the primary side series resonance current Io flows in a sine wave as seen in FIG. 24, and within a period within which the sawtooth waveform component by the exciting inductance flows as the primary side series resonance current Io within the period, the secondary winding voltage V2 exhibits the 0 level. A waveform reversed from the secondary winding voltage V2 is generated in the secondary winding N2B.
Therefore, the rectification current I1 flowing through the rectification diode Do1 and the rectification current I2 flowing through the rectification diode Do2 flow only within the periods DON1, DON2 within which the primary side series resonance current Io flows in a sine wave, but do not flow within any other period. In other words, the rectification current on the secondary side flows discontinuously into the smoothing capacitor.
It is to be noted that the level of the secondary side dc output voltage Eo is inclined to vary also in response to the level of the commercial ac power supply AC (ac input voltage VAC) and variable control of the switching frequency responsive to the variation is performed, and therefore, also the variation of the commercial ac power supply AC may possibly make a cause of establishment of the discontinuous mode described above.
Further, since the voltage drop in the forward direction of the rectification diodes Do1, Do2 which are Schottky diodes is 0.6 volts and, in such operation of the secondary side as described above, the rectification currents I1, I2 exhibit a considerably high level of 35 Ap, the continuity loss by the rectification diodes appears conspicuously, resulting in increasing power loss.
According to a result of the actual measurement, the DC to DC power conversion efficiency when the dc input voltage (rectified smoothed voltage Ei)=100 V is approximately 82% to the utmost.
Thus, as a technique for reducing the continuity loss of rectification current on the secondary side, a synchronous rectification circuit is known wherein a MOS-FET having low on resistance is used for rectification. An example of a configuration of a synchronous rectification circuit of the type described which uses a winding voltage detection system is shown in FIG. 25.
It is to be noted that, in FIG. 25, a configuration only of the secondary side of an insulating converter transformer PIT is shown. The primary side has a configuration similar to that shown in FIG. 23. Further, as a constant voltage control system, a switching frequency control system is used wherein the switching frequency of the primary side switching converter is variably controlled in response to the level of the secondary side dc output voltage Eo.
Further, also the power supply circuit having the secondary side shown in FIG. 25 is ready for the conditions of low voltage and high current (VAC=100 V, load power Po=100 W, Eo=5 V and Io=25 A) similar to those in the case of FIG. 23.
Also in this instance, the secondary windings N2A, N2B of the secondary winding having numbers of turns each to each other are connected at one ends thereof to each other by a center tap, and the center tap output is connected to the positive terminal of the smoothing capacitor Co. The other end of the secondary winding N2A is connected to the secondary side ground (negative terminal side of the smoothing capacitor Co) through the drain-source of an N-channel MOS-FET Q3. Similarly, the other end of the secondary winding N2B is connected to the secondary side ground (negative terminal side of the smoothing capacitor Co) through the drain-source of an N-channel MOS-FET Q4. In short, in this instance, the MOS-FETs Q3, Q4 are inserted in series to the negative electrode side in the rectification current paths of the secondary windings N2A, N2B, respectively. It is to be noted that body diodes DD3, DD4 are connected to the drains—sources of the MOS-FETs Q3, Q4, respectively.
A drive circuit for driving the MOS-FET Q3 includes a gate resistor Rg1 connected between a node between the secondary winding N2B and the drain of the MOS-FET Q4 and the gate of the MOS-FET Q3, and a resistor R11 connected between the gate of the MOS-FET Q3 and the secondary side ground.
Similarly, a drive circuit for driving the MOS-FET Q4 includes a gate resistor Rg2 connected between a node between the secondary winding N2A and the drain of the MOS-FET Q3 and the gate of the MOS-FET Q4, and a resistor R12 connected between the gate of the MOS-FET Q4 and the secondary side ground.
If an on voltage is applied to the gate of a MOS-FET, then the drain-source becomes equivalent to a mere resistor, and therefore, current can flow in the opposite directions. If it is tried to cause the MOS-FET to function as a rectification element on the secondary side, then current must flow only in the direction in which the positive electrode of the smoothing capacitor Co is charged. If current flows in the reverse direction, then discharge current flows from the smoothing capacitor Co to the insulating converter transformer PIT side, and therefore, power cannot be transmitted efficiently to the load side. Further, the reverse current gives rise to generation of heat by the MOS-FET or to production of noise and also to switching loss on the primary side.
The drive circuit described above is provided for driving the MOS-FETs Q3, Q4 to switch so that current flows only in the direction in which the positive electrode terminal of the smoothing capacitor Co is charged based on detection of the voltage of the secondary winding.
A waveform diagram of FIG. 26 illustrates operation of the power supply circuit having the configuration of the secondary side shown in FIG. 25 (and the configuration of the primary side similar to that shown in FIG. 23) when the load power Po is Po=100 W. As described hereinabove, the load power Po=100 W in this instance is a substantially maximum load condition.
Referring to FIG. 26, the voltage V1 across the switching element Q2 and the corresponding secondary winding voltage V2 across the opposite ends of the secondary windings N2A–N2B exhibit timings similar to those of FIG. 24. It is to be noted that the secondary winding voltage V2 illustrated in FIG. 26 has the polarity where it is viewed from the node side between the secondary winding N2A and the gate resistor Rg2, and if it is viewed from the node side between the secondary winding N2B and the gate resistor Rg1, then the secondary winding voltage V2 has the opposite polarity.
The drive circuit for the MOS-FET Q4 operates such that, when the secondary winding voltage V2 of the polarity shown in FIG. 26 comes to a period within which it is to be clamped with a predetermined level of the negative polarity, the drive circuit applies an on voltage of a level which is set by the gate resistor Rg2 and the resistor R12 to the gate of the MOS-FET Q4.
Similarly, the drive circuit (gate resistor Rg1 and resistor R11) for the MOS-FET Q3 operates such that, when the secondary winding voltage (V2) of the polarity reverse to that shown in FIG. 26 comes to a period within which it is to be clamped with a predetermined level of the negative polarity, the drive circuit applies an on voltage to the gate of the MOS-FET Q3.
Consequently, the rectification currents I1, I2 of the positive polarity flow through the MOS-FETs Q3, Q4 within periods DON1, DON2 as seen in FIG. 26, respectively. The rectification currents I1, I2 flowing within a period within which the secondary winding voltage V2 illustrated in FIG. 26 is clamped in the positive/negative are approximately 35 Ap similarly as in the case of the circuit of FIG. 23 (rectification currents I1, I2 of the waveform diagram of FIG. 24). However, the MOS-FETs Q3, Q4 have low on resistance, and the continuity loss of rectification current by the MOS-FETs Q3, Q4 can be reduced significantly when compared with the rectification diodes Do1, Do2 each formed from a Schottky diode. Further, as can be recognized also from the fact that the drive circuit is composed only from resistance elements, the winding voltage detection method is advantageous also in that the drive circuit system is simple in configuration.
However, in such a heavy load (load power Po=100 W) condition as in the case of FIG. 26, also the secondary side rectification current of the power supply circuit exhibits a discontinuous mode. This is indicated by the fact that the periods DON1, DON2 in FIG. 26 are discontinuous.
In the discontinuous mode, even if the charging current as the rectification currents I1, I2 to the smoothing capacitor Co decreases to the 0 level, current flows in the same direction through the primary winding N1 of the insulating converter transformer PIT. In the case of the waveform diagram of FIG. 24, this is indicated by the fact that the exciting inductance component of the primary winding N1 in the primary side series resonance current Io flows with the same polarity as that at the immediately preceding timing. Consequently, since actually the polarities of voltages induced in the secondary windings N2A, N2B are not reversed, the MOS-FETs Q3, Q4 maintain an on state without being placed into a completely off state. As a result, the rectification currents I1, I2 flow as currents of the reverse direction within the other periods than the periods DON1, DON2. Although the rectification currents I1, I2 of the reverse direction within the other periods than the periods DON1, DON2 provide reactive power, since the levels of the rectification currents I1, I2 are approximately 8 Ap and comparatively high, also the reactive energy exhibits a corresponding high level.
In this manner, where the synchronous rectification circuit employs the winding voltage detection system, although the continuity loss of rectification current decreases, since reactive power is generated in such a manner as described above, it is generally difficult to achieve effective improvement of the power conversion efficiency.
A waveform diagram of FIG. 27 illustrates operation of the power supply circuit having the secondary side configuration shown in FIG. 25 under a light load condition.
In an actual form of the power supply circuit shown in FIG. 25, constant voltage control by switching frequency control is performed as described above in connection with the configuration of the power supply circuit shown in FIG. 23. However, if a light load condition is entered and the secondary side dc output voltage rises, then the switching frequency is raised to lower the secondary side dc output voltage. The power supply circuit thereby operates so as to achieve stabilization.
In such a light load condition as described above, the secondary winding voltage V2 reverses at a substantially same timing as that of the voltage V1 across the switching element Q2 illustrated in FIG. 27. In response to this, the rectification currents I1, I2 flow such that they continuously charge the smoothing capacitor Co without any rest period between the periods DON1, DON2. In other words, a continuous mode is obtained. At this time, such a period within which the rectification currents I1, I2 flow in the reverse direction as described as the operation in the heavy load condition with reference to FIG. 26 does not exist any more, and no corresponding reactive power is generated.
In this manner, also the power supply circuit of the configuration wherein the secondary side rectification circuit system is replaced by the synchronous rectification circuit according to the winding voltage detection method still has the problem of a drop of the power conversion efficiency upon the heavy load operation.
As a technique for eliminating the problem of generation of reactive power by rectification current in the reverse direction as seen from FIG. 26, a synchronous rectification circuit according to the rectification current detection system is known. The rectification current detection system is a technique wherein the MOS-FET is turned off before the rectification current charged into the smoothing capacitor Co decreases to the zero level.
An example of a configuration of a synchronous rectification circuit according to the rectification current detection system is shown in FIG. 28. It is to be noted that, in FIG. 28, a configuration which performs half-wave rectification is shown for simplified illustration and description.
In the rectification current detection system, a current transformer TR is provided for detecting current flowing through a secondary winding N2. A primary winding Na of the current transformer TR is connected to an end portion of the secondary winding N2 and the drain of the MOS-FET Q4. The source of the MOS-FET Q4 is connected to the negative electrode terminal of a smoothing capacitor Co.
A resistor Ra is connected in parallel to a secondary winding Nb of the current transformer TR. Further, diodes Da, Db are connected in parallel to the secondary winding Nb such that the forward voltage directions thereof may be opposite to each other to form a parallel connection circuit. A comparator 20 is connected to the parallel connection circuit. A reference voltage Vref is inputted to the negated input of the comparator 20. It is to be noted that an end portion of the parallel connection on the side to which the anode of the diode Da and the cathode of the diode Db are connected is connected to a node between the reference voltage Vref and the negated input of the comparator 20. On the other hand, the opposite end portion of the parallel connection circuit to which the cathode of the diode Da and the anode of the diode Db are connected is connected to the non-negated input of the comparator 20.
In this instance, the output of the comparator 20 is amplified by a buffer 21 and applied to the gate of the MOS-FET Q4.
Operation of the circuit having the configuration shown in FIG. 28 is illustrated in FIG. 29.
If a voltage induced in the secondary winding N2 becomes higher than a voltage (Eo) across the smoothing capacitor Co, then rectification current Id first begins to flow in the anode→cathode direction of the body diode of the MOS-FET Q4 so as to charge the smoothing capacitor Co. Since the rectification current Id flows to the primary winding Na of the current transformer TR, a voltage Vnb corresponding to the rectification current Id flowing through the primary winding Na is induced in the secondary winding Nb of the current transformer TR. The comparator 20 compares the voltage Vnb with the reference voltage Vref and outputs the H (high) level if the voltage Vnb is higher than the reference voltage Vref. The output of the H level is applied as an on voltage to the gate of the MOS-FET Q4 from the buffer 21 to turn on the MOS-FET Q4. Consequently, the rectification current Id flows in the drain→source direction of the MOS-FET Q4. In FIG. 29, it is shown that the rectification current Id flows with the positive polarity.
Then, when the level of the rectification current Id drops in response to lapse of time and the voltage Vnb becomes equal to or lower than the reference voltage Vref in response to the drop of the level of the rectification current Id, the comparator 20 reverses the output thereof. The reversed output is outputted through the buffer 21 to cause the gate of the MOS-FET Q4 to discharge thereby to turn off the MOS-FET Q4. It is to be noted that, at this point of time, the remaining rectification current Id flows in a short period of time through a body diode DD4.
As a result of such operation as described above, the MOS-FET Q4 is turned off at a timing before the rectification current Id decreases to the 0 level. Consequently, such a situation that reverse direction current flows through the MOS-FET within a period within which the rectification current is discontinuous as seen in FIG. 26 is eliminated, and no reactive power is generated. Consequently, the power conversion efficiency rises as much.
For example, the dc→dc power conversion efficiency where the synchronous rectification circuit according to the rectification current detection system of full-wave rectification and based on the configuration described hereinabove with reference to FIG. 28 was used as the configuration of the secondary side of the power supply circuit shown in FIG. 23 was measured under conditions similar to those described hereinabove with reference to FIG. 24 or 26. From the measurement, a result was obtained that the dc→dc conversion efficiency is improved to approximately 90%.
However, with the synchronous rectification circuit of the rectification current detection system described above, at least one current transformer corresponding to one MOS-FET and a comparatively complicated drive circuit system for driving the MOS-FET with an output of the current transformer are required as can be recognized also from FIG. 28. Consequently, the circuit configuration is complicated, and this gives rise to a disadvantage in that it causes drop of the production efficiency, increase of the cost, expansion of the size of a circuit board and so forth.
Particularly where the configuration of the switching converter on the primary side shown in FIG. 23 is used as a basic configuration and a synchronous rectification circuit of the rectification current detection system is provided on the secondary side, it is necessary to provide a full-wave rectification circuit on the secondary side. Accordingly, two sets of such a current transformer and a drive circuit system as described above are required individually corresponding to the MOS-FETs Q3, Q4, and this makes the problem described above further serious.
In this manner, between the winding voltage detection system and the rectification current detection system, the winding voltage detection system is less advantageous in terms of the power conversion efficiency because of reactive power, but is simple in the circuit configuration. In contrast, the rectification current detection system is more advantageous in terms of the power conversion efficiency because no reactive power is generated, but is complicated in the circuit configuration. In this manner, the two methods have the mutually tradeoff relationship.
Accordingly, it is demanded that a power supply circuit which includes a synchronous rectification circuit be configured so that increase of the loss by reactive power may be eliminated while the circuit configuration is as simple as possible.